The present invention relates a binary VLSI (Very Large Scale Intergration) multiplier device capable of multiplying operands with a large number of bits.
A conventional microprocessor in carrying out multiplication on, say, two 32 bit operands uses 32 clock signals as well as software programming. An alternate approach is to utilize hardware rather than software in addition to microprogramming. A standard hardware approach is to use an add-shift method in which each partial product is shifted one position to the left and then added to an accumulated sum of previously computed partial products. For 32 bit operands this method requires 32 different addition steps in calculating the accumulated sum of partial products. Considering that a large proportion of the delay in passing through a multiplier occurs in the adder, the foregoing method is relatively slow. This number of steps can be reduced substantially by partitioning the multiplier into a selected number of segments, say "m" partial products. This reduction in the number of partial products results in a faster multiplication operation although additional overhead cycles are required to load the different versions of the multiplicand into a local store.
An even faster approach is a one-step combinational planar array multiplier. In this case the bits of the operands are partitioned into high order and low order bits and the partial products formed into four groups corresponding to the four groupings of the high and low order bits termed non-additive multiply modules (NMM's). Each group of NMM's is sent to a corresponding array of combinational AND circuits which output the individual product terms of each NMM. Some of these product terms are directed to bit-slice carry-save adders, known as Wallace trees which produce the sum of the inputs. Alignment of the subproducts is accompanied by inputting them to the appropriate Wallace tree. The sum and carry outputs from each Wallace tree are sent to a conventional binary adder with carry lookahead, which merges the two outputs into the final output.
Accordingly, it is an object of the present invention to provide an improved multiplier circuit. It is a further object of the invention to provide a multiplier circuit in which the accumulator is part of partial product summing loop. Yet a further object of the invention is to provide a multiplier array in which a register is optionally bypassed for flowthrough operation.